An ultra low power implantable neural recording system for brain-machine interfaces

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2011.Cataloged from PDF version of thesis.Includes bibliographical references (p. 179-187).In the past few decades, direct recordings from different areas of the brain have enabled scientists to gradually understand and unlock the secrets of neural coding. This scientific advancement has shown great promise for successful development of practical brain-machine interfaces (BMIs) to restore lost body functions to patients with disorders in the central nervous system. Practical BMIs require the uses of implantable wireless neural recording systems to record and process neural signals, before transmitting neural information wirelessly to an external device, while avoiding the risk of infection due to through-skin connections. The implantability requirement poses major constraints on the size and total power consumption of the neural recording system. This thesis presents the design of an ultra-low-power implantable wireless neural recording system for use in brain-machine interfaces. The system is capable of amplifying and digitizing neural signals from 32 recording electrodes, and processing the digitized neural data before transmitting the neural information wirelessly to a receiver at a data rate of 2.5 Mbps. By combining state-of-the-art custom ASICs, a commercially-available FPGA, and discrete components, the system achieves excellent energy efficiency, while still offering design flexibility during the system development phase. The system's power consumption of 6.4 mW from a 3.6-V supply at a wireless output data rate of 2.5 Mbps makes it the most energy-efficient implantable wireless neural recording system reported to date. The system is integrated on a flexible PCB platform with dimensions of 1.8 cm x 5.6 cm and is designed to be powered by an implantable Li-ion battery. As part of this thesis, I describe the design of low-power integrated circuits (ICs) for amplification and digitization of the neural signals, including a neural amplifier and a 32-channel neural recording IC. Low-power low-noise design techniques are utilized in the design of the neural amplifier such that it achieves a noise efficiency factor (NEF) of 2.67, which is close to the theoretical limit determined by physics. The neural recording IC consists of neural amplifiers, analog multiplexers, ADCs, serial programming interfaces, and a digital processing unit. It can amplify and digitize neural signals from 32 recording electrodes, with a sampling rate of 31.25 kS/s per channel, and send the digitized data off-chip for further processing. The IC was successfully tested in an in-vivo wireless recording experiment from a behaving primate with an average power dissipation per channel of 10.1 [mu]W. Such a system is also widely useful in implantable brain-machine interfaces for the blind and paralyzed, and in cochlea implants for the deaf.by Woradorn Wattanapanitch.Ph.D

An ultra-low-power neural recording amplifier and its use in adaptively-biased multi-amplifier arrays

Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2007.Includes bibliographical references (p. 99-101).The design of a micropower energy-efficient neural recording amplifier is presented. The amplifier appears to be the lowest power and most energy-efficient neural recording amplifier reported to date. I describe low-noise design techniques that help the neural amplifier achieve an input-referred noise that is near the theoretical limit of any amplifier using a differential pair as an input stage. The bandwidth of the amplifier can be adjusted for recording either neural spikes or local field potentials (LFP). When configured for recording neural spikes, the amplifier yielded a midband gain of 40.8 dB and -3 dB bandwidth from 45 Hz to 5.32 kHz; the amplifier's input-referred noise was measured to be 3.06 [mu]Vrms, while consuming 7.56 [mu]W of power from a 2.8 V supply corresponding to a Noise Efficiency Factor (NEF) of 2.67 with the theoretical limit being 2.02. When configured for recording LFPs, the amplifier achieved a midband gain of 40.9 dB and a -3 dB bandwidth from 392 mHz to 295 Hz; the input-referred noise was 1.66 [mu]Vrms, while consuming 2.08 AW from a 2.8 V supply corresponding to an NEF of 3.21. The amplifier was fabricated in AMI's 0.5 im CMOS process and occupies 0.16 mm2 of chip area. The designs of two previous amplifiers that have been attempted are also presented. Even though they do not achieve optimal performances, the design insights obtained have led to a successful implementation of the energy-efficient neural amplifier discussed above.(cont.) Finally, the adaptive biasing technique is discussed. The design and the detailed analysis of a feedback calibration loop for adjusting the input-referred noise of the amplifier based on the information extracted from the recording site's background noise is also presented. With such an adaptive biasing scheme, significant power savings in a multi-electrode array may be achieved since each amplifier operates with just enough power such that its input-referred noise is significantly but not overly below the neural noise.by Woradorn Wattanapanitch.S.M

Efficient Universal Computing Architectures for Decoding Neural Activity

The ability to decode neural activity into meaningful control signals for prosthetic devices is critical to the development of clinically useful brain– machine interfaces (BMIs). Such systems require input from tens to hundreds of brain-implanted recording electrodes in order to deliver robust and accurate performance; in serving that primary function they should also minimize power dissipation in order to avoid damaging neural tissue; and they should transmit data wirelessly in order to minimize the risk of infection associated with chronic, transcutaneous implants. Electronic architectures for brain– machine interfaces must therefore minimize size and power consumption, while maximizing the ability to compress data to be transmitted over limited-bandwidth wireless channels. Here we present a system of extremely low computational complexity, designed for real-time decoding of neural signals, and suited for highly scalable implantable systems. Our programmable architecture is an explicit implementation of a universal computing machine emulating the dynamics of a network of integrate-and-fire neurons; it requires no arithmetic operations except for counting, and decodes neural signals using only computationally inexpensive logic operations. The simplicity of this architecture does not compromise its ability to compress raw neural data by factors greater than . We describe a set of decoding algorithms based on this computational architecture, one designed to operate within an implanted system, minimizing its power consumption and data transmission bandwidth; and a complementary set of algorithms for learning, programming the decoder, and postprocessing the decoded output, designed to operate in an external, nonimplanted unit. The implementation of the implantable portion is estimated to require fewer than 5000 operations per second. A proof-of-concept, 32-channel field-programmable gate array (FPGA) implementation of this portion is consequently energy efficient. We validate the performance of our overall system by decoding electrophysiologic data from a behaving rodent.United States. National Institutes of Health (Grant NS056140

Low-Power Circuits for Brain–Machine Interfaces

This paper presents work on ultra-low-power circuits for brain–machine interfaces with applications for paralysis prosthetics, stroke, Parkinson’s disease, epilepsy, prosthetics for the blind, and experimental neuroscience systems. The circuits include a micropower neural amplifier with adaptive power biasing for use in multi-electrode arrays; an analog linear decoding and learning architecture for data compression; low-power radio-frequency (RF) impedance-modulation circuits for data telemetry that minimize power consumption of implanted systems in the body; a wireless link for efficient power transfer; mixed-signal system integration for efficiency, robustness, and programmability; and circuits for wireless stimulation of neurons with power-conserving sleep modes and awake modes. Experimental results from chips that have stimulated and recorded from neurons in the zebra finch brain and results from RF power-link, RF data-link, electrode- recording and electrode-stimulating systems are presented. Simulations of analog learning circuits that have successfully decoded prerecorded neural signals from a monkey brain are also presented

A biomimetic adaptive algorithm and low-power architecture for decoders

Algorithmically and energetically efficient computational architectures that operate in real time are essential for clinically useful neural prosthetic devices. Such devices decode raw neural data to obtain direct control signals for external devices. They can also perform data compression and vastly reduce the bandwidth and consequently power expended in wireless transmission of raw data from implantable brain-machine interfaces. We describe a biomimetic algorithm and micropower analog circuit architecture for decoding neural cell ensemble signals. The decoding algorithm implements a continuous-time artificial neural network, using a bank of adaptive linear filters with kernels that emulate synaptic dynamics. The filters transform neural signal inputs into control-parameter outputs, and can be tuned automatically in an on-line learning process. We provide experimental validation of our system using neural data from thalamic head-direction cells in an awake behaving rat.National Eye Institute (grant R01-EY13337)United States National Institutes of Health (grants R01-NS056140 and R01-EY15545)McGovern Institute for Brain Research at MIT. Neurotechnology (MINT) Progra

Histograms and Threshold.

<p>Histograms collected during the training phase of the decoding algorithm facilitate computation of thresholds for windowed spike activity, which are stored as templates in memory and used to discriminate between states. This histogram of spike activity, collected from recording channel , demonstrates that a threshold of spikes per -ms window, on recording channel , is sensitive and specific for state (Sensitivity: , Specificity: , Positive Predictive Value: ). This threshold is written on the threshold tape used to program the internal unit of the decoder, and can be seen numerically in <a href="http://www.plosone.org/article/info:doi/10.1371/journal.pone.0042492#pone-0042492-g004" target="_blank">Figure 4</a> as the and row entries of column , and graphically as the corresponding pixels in the rule array.</p

Decoder Logic Program: Finite-State Automaton Rules for Neural Decoding.

<p>Decoding template array stored in system memory, resulting in the output shown in <a href="http://www.plosone.org/article/info:doi/10.1371/journal.pone.0042492#pone-0042492-g005" target="_blank">Figure 5</a>, using the most informative threshold values for each position state. Some elements of the rule table (three pair) are empty, with corresponding columns having fewer than nonwhite elements, because the associated states had fewer than channels able to satisfy and , the minimum sensitivity and positive predictive value, respectively, for state decoding. (White: Unused, Light Gray: Spike per -ms Window, Black: Spikes per -ms Window.) Intuitively, this set of templates can be understood as the tape-reading rules for a Turing machine, whose symbols are generated by the time-windowed spike counts on neural input channels, and whose states correspond to a discretized set of position states encoded by the underlying neuronal populations. At each time step, the neural decoder scans down each column in the array to determine the states, if any, whose rules have been satisfied; the decoded output elements are set to for those states, and to otherwise. The rules displayed graphically in the rectangular array are encoded numerically in the table displayed above the array (which is reproduced in <a href="http://www.plosone.org/article/info:doi/10.1371/journal.pone.0042492#pone-0042492-t001" target="_blank">Table 1</a>). The columns of the table are aligned with the states in the array for which they contain decoding data, comprising the indices of the two most informative channels, and , and the corresponding spike thresholds, and .</p

Decoding Architecture.

<p>Block diagram of the low-power processing system of the internal component of our neural decoder, as implemented in one instantiation of our architecture. Functional blocks are color-coded in accord with the scheme used in <a href="http://www.plosone.org/article/info:doi/10.1371/journal.pone.0042492#pone-0042492-g001" target="_blank">Figure 1</a>.</p

Encoding of Position by Place Cell Receptive Fields.

<p>Normalized spike rate for each of neurons in equal-length intervals along a one-dimensional track maze. Neurons (rows) have been sorted according to their positions of maximal activity to illustrate that the receptive fields of the place cells in this population cover the one-dimensional space of interest. Neuronal spike rates for each cell in each state (row elements) have been normalized to the highest spike rate (maximal row element) exhibited by the particular cell over all states. (Black: Maximal Spike Rate, White: Zero Spike Rate, Gray: Intermediate Spike Rates.).</p